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Issues: ucb-bar/chiseltest

47 Open 147 Closed
47 Open 147 Closed
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Issues list

Line coverage report fails with VerilatorBackend bug Something isn't working
#735 opened Jun 28, 2024 by PhilippKasgen
1
Implement SytemVerilog style Sequences
#733 opened Jun 17, 2024 by Gallagator
1
Cover is not yet implemented for Chiseltest
#732 opened Jun 17, 2024 by Gallagator
3
Solver Chosen Constants for Formal Verification
#664 opened Aug 6, 2023 by fayalalebrun
3
Report assert message with FailedBoundedCheckException
#652 opened Jun 30, 2023 by yupferris
1
JRE detects EXCEPTION_ACCESS_VIOLATION when trying to use Verilator as Chiseltest's backend
#649 opened Jun 25, 2023 by hiroshi-ya
2
Proving formal properties
#648 opened Jun 20, 2023 by yupferris
4
Checking formal properties over multiple tests
#647 opened Jun 20, 2023 by yupferris
2
poke in ChiselScalatestTester occurs on falling clock edge in traces
#646 opened Jun 19, 2023 by yupferris
4
TODO: implement plusarg intrinsic support for all supported simulators and formal verification
#638 opened Jun 9, 2023 by ekiwi
Confused by fork.withRegion(Monitor)
#630 opened Apr 25, 2023 by mvanbeirendonck
@ducky64
1
Confusing Fork-Join Usage
#627 opened Mar 28, 2023 by liuxd17thu
2
chiseltest recognisez $finish in verilog fails
#626 opened Mar 23, 2023 by pxs7
Function loadMemoryFromFile failed in chiseltest
#621 opened Feb 20, 2023 by B10615053
2
Fsdb annotation method needs to be update
#592 opened Dec 31, 2022 by KyleJeong
Chisel formal needs simple examples (README)
#562 opened Oct 20, 2022 by schoeberl
memory leak?
#557 opened Sep 26, 2022 by schoeberl
5
FlatIO is not supported
#527 opened Apr 28, 2022 by oharboe
@jackkoenig
Feature request: Always advance clock by one cycle at the end of failed tests
#516 opened Apr 14, 2022 by KasperHesse
6
feature request: PSL support for formal verification. feature request
#416 opened Oct 21, 2021 by Martoni
1
Feature request - cache elaboration across tests feature request
#380 opened Aug 18, 2021 by oharboe
Update the chisel-lang documentation for this project
#352 opened Aug 5, 2021 by chick
@chick @ekiwi
3
Tests hang: possible race condition
#285 opened Mar 30, 2021 by kammoh
@ducky64
4
TopLevel output port cannot have inferred width if testing with verilator bug Something isn't working
#257 opened Jan 5, 2021 by chick 0.5.0
Poke for internal registers
#215 opened Oct 15, 2020 by danielkasza
1
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