Feature/rmii 100M rt #70
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…rmii_100m_rt * commit '02343159640e8d46ba929d86c8c37cae0e9c45ac': Update test_support hash Use Xsi.get_xsi_tick_freq_hz() in timeout calculation Update tests/helpers.cmake Use custom test_support branch. Remove hardcoded xsi tick freq from tests Hardcode seed to 1 in test_avb_traffic.py. Update changelog and copyright Run tests with or without --seed based on Jenkinsfile parameter Add comments to shaper Renamed test ids in test_rx_queues.py Modified conftest.py to set the seed Added a --seed option to pytest to allow tests to run with a fixed seed Use custom branch for test_support Get test_shaper passing Fixed _max_mbps calculation in DataLimiter.get_ifg(). Increased END_OF_TEST_TIME to avoid test time outs. Re-enabled RGMII 125MHz group a and b tests Port more tests to xs3 architecture Test for xs3 architecture
…on of the self._period
…t into feature/rmii_100m_rt
…t into feature/rmii_100m_rt * 'feature/rmii_100m_rt' of github.com:ed-xmos/lib_ethernet: run rmii_rx (loopback) test with all combinations of tx and rx widths In the MII Clock class, define self._bit_time as a divided down version of the self._period
…AS_REF_CLOCK_COUNT_4b to get 96 bit time IFG
…t into feature/rmii_100m_rt
* feature/rmii_100m_rt: Comment and local test prog buffer size Extend test_tx.py to run rmii configs Added filler threads in test_rmii_tx and test_rmii_rx Simplify preamble check logic 1b rx Don't assum num_rx_bytes in 1b rx Bring rx_1b into inline while(1) select for performance Remove MASTER_RX_CHUNK_TAIL/HEAD macros # Conflicts: # lib_ethernet/src/rmii_master.xc
…t into feature/rmii_100m_rt
* feature/asm_wrap_rx: Tidy only Implement buffer write checking in ASM WIP update ASM Test program self checks Add nop slots into ASM and run at 350MHz
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Add RMII (2b data @ 50MHz) version of the RT 100M MAC.